搜索资源列表
SHA1_TOP
- sha_1加密运算模块,运算速率100Mbps,规格512位请大家参考-encryption algorithms sha_1 module, computing rate of 100Mbps, the specifications please refer to 512
DESHTM
- 用VHDL语言实现了DES加密算法,其中包含了测试程序,能够进行仿真。-Using VHDL language implementation of the DES encryption algorithm, which contains the test procedures can be simulated.
sha
- sha加密算法实现,经过FPGA验证的!-sha encryption algorithm, after FPGA validation!
GF_MUL
- Galois域乘法器的Verilog源码 广泛用于信道编码、计算机代数及椭圆曲线加密等-Galois field multipliers are widely used in the Verilog source channel coding, computer algebra and elliptic curve encryption
3DES
- fpga3des加密非常有用 希望大家喜-fpga3des
DES
- DES加密算法的VHDL实现,采用流水线技术实现-The VHDL implement of DES encrypt algorithmic
hundunjiami
- 混沌加密应用于实际电路的VHDL语言编写的电路选通程序。-Chaotic encryption used in the actual circuit of the circuit VHDL language gating process.
tripledes
- 3-DES加密IP核VHDL源码,3次DES流水执行-VHDL source code for 3-DES encryption IP core, pipelined execution
aes
- 实现了AES在赛灵思器件上的加密程序 我已经调试过完全正确-Xilinx achieved in AES encryption device debugging process I have been absolutely correct
rsa
- 用VHDL求rsa加密系统的密钥D(辗转相除法)-Using VHDL for rsa key encryption system D(Division algorithm)
DESCryptographicAlgorithm
- des加密算法,用于IP通讯方面的,用VHDL写成的源程序-des encryption algorithm used for IP communications.the source codes are written in VHDL
vongrunigen
- 语音信号处理,关于语音加密和解密的一个例子-Speech signal processing, voice encryption and decryption on an example of
systemcaes_latest.tar
- 高级加密标准aes加密算法用fpga实现的Verilog源代码。-Advanced encryption standard aes encryption algorithm using fpga implementation Verilog source code.
Chapter1-5
- 第一章到第五章的代码 本书通过100多个模块实例,详细地讲解了Verilog HDL程序设计语言,全书共分13章,内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等,实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例
Chapter11-13
- 第十一章到第十三章的代码 本书通过100多个模块实例,详细地讲解了Verilog HDL程序设计语言,全书共分13章,内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等,实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个
m
- m序列信号发生器的设计,用于保密通信,和信息加密,属于流密码。-m sequence signal generator designed for confidential communications, and information encryption, part of stream ciphers.
aes
- 高级加密标准AES的FPGA实现,支持128,256密钥长度格式-Advanced Encryption Standard AES, FPGA implementation to support 128,256 key length format
DES-HDL
- 用HDL实现的DES加密算法,通过前仿真,希望对大家有帮助-HDL implementation of the DES with the encryption algorithm, by pre-simulation, we want to help
Logistichecat
- 将猫映射(cat map ) 与Logist ic 映射相结合, 构造了一种语音加密算法. 该算法首先将语音数据堆叠成二维, 然后利用二维猫映射将数据的位置置乱, 最后利用一维Logist ic 映射构造替换表, 对数据进行扩散.-The cat map (cat map) and Logist ic mapping the combination of a voice encryption algorithm is constructed. The algorithm first voic
DES_Encrypt_Decrypt_Verilog
- DES加密算法的Verilog HDL实现,带模式选择端口,可以实现加密和解密,已经modelsim仿真通过。-Des En/Decrypt,Verilog HDL code